Broadcom Debuts Single Chip for Headend Data


Continuing on a rapid integration track, Broadcom Corp.
last week started shipping sample quantities of a single-chip solution for cable-modem

The new chip -- the BCM 3137 -- is supposed to dramatically
reduce the manufacturing cost of cable-modem headends, while yielding large increases in
the amount of data or number of simultaneous users that can be supported in upstream,
home-to-headend data configurations.

Broadcom officials said the chip, which had been configured
as 10 separate chips in a field-programmable gate array, passed through
cable-modem-interoperability tests last month, making it compatible with the DOCSIS (Data
Over Cable Service/Interoperability Specification) standard.

What makes the chip different from the earlier Broadcom
FPGA set is the addition of 16-QAM (quadrature amplitude modulation) for upstream
communications, in addition to previously available QPSK (quadrature phase shift key)
techniques common to DOCSIS.

"It represents an enormous reduction in cost,"
said Tim Lindenfelser, vice president of marketing for Broadcom, explaining that the
previous FPGA board in use by cable-modem-headend producers like Cisco Systems Inc., Bay
Networks Inc., 3Com Corp. and others cost about $3,000, while the BCM 3137 is
sample-priced at $200.

The chip is backward-compatible with cable-modem-headend
equipment already installed in MSO headends, he said, and it supports four to eight
upstream channels per card, instead of one.

"This is a chip that has been long anticipated from
the cable-modem community, because it offers an enormous performance upgrade,"
Lindenfelser said.

That's because running upstream communications with
16-QAM modulation -- which is also frequency-agile, so that data can be moved to a safer
frequency during noise spikes -- enables upstream data rates of 20 megabits per second.
QPSK, in contrast, runs at 10 mbps.

Notably, a big question is whether or not the 5- to
40-megahertz upstream cable path can shoulder the extra speed, said Michael Harris, an
analyst with Phoenix-based Kinetic Strategies Inc. Because the upstream-signal path is
inherently the home for ingress and impulse noise, plant must be in "pretty clean
condition" to support 20-mbps communications, he added.

Lindenfelser said the inclusion of forward-error
correction, a data interleaver and rate-adaptive capabilities -- so that the headend knows
to slow down data transmissions in the presence of noise -- translates into a need for
about 14 to 16 decibels of carrier-to-noise ratio in the upstream-signal path.

"The whole approach here is noise avoidance,"
Lindenfelser said. "If there's ingress, the headend chip moves the transmission
channels around or throttles back to lower rates."

The 3137 chip shipped in sample quantities last week, and
it is currently available in "production quantities," executives said.